KiCad was my most-used electronic design automation (EDA) software suite in 2025. And while I and many other electrical engineers have tried other EDA tools over the years, KiCad’s gradual improvements have earned it a bit of a cult following.
This, in my opinion, was especially true after KiCad 6, when the development team addressed two key problems that were holding the project back. The first was the many design idiosyncrasies and counterintuitive controls that once made the project unapproachable for some. For example, copy-paste didn’t exist when I started using the suite and instead had an awkward “duplicate” procedure that disoriented users expecting a drag-and-drop experience. Cryptically named eeschema and “PcbNew” were relabeled simply “Schematic Editor” and “PCB Editor,” respectively, showing a deeper commitment to plain language—or at least terminology considered plain within the industry.
But the biggest improvement over the years was the revamping of the save file system. Now, whole files, along with the very components and objects on the canvas, are represented using human-readable S-expression object notation. The result was an auditable file format that was self-contained, making it easy to transfer work between computers.
So what’s in store for KiCad 10? Having been recently released on March 20, 2026, the best way to check is to back up any old KiCad files and try it for yourself. Note that KiCad installations will automatically attempt to modernize any file you instruct them to save, which can work against you if you ever need an older version of KiCad to open the updated file. But there are a few key features in KiCad that I’m eager to see added or refined in some way, even if they’re not immediately addressed.
BUS RETOOLING
By far, the most counterintuitive feature I’ve encountered since KiCad version 5 is the bus feature. For context, many electrical schematics cluster similar wires or signals together into a single unit. Traditionally, that is done by depicting the group as a line that is notably thicker than a standard wire, or at least a different color. Imagine the sheer mess of drawing the individual wires of a 24-bit parallel data bus while needing them to snake across entire drawings.
Ultimately, buses are a visual aid that de-clutters drawings and depicts group-member relationships with ease. This is where things get a tad awkward for users. Buses themselves can be drawn at any time, but their member nets must be defined using net labels first. Then, and only then, can the individual member nets be off-ramped or “unfolded” from the bus.
KiCad 9 offers four ways to deal with buses. However, each one requires you to place a specially formatted label on the bus in order to define the nets it carries. This contrasts with other schematic capture tools, where nets can simply be drawn into or out of the bus using on-ramps—or unfolds, as they are called in KiCad.
FOOTPRINT-FREE NET TIE
Often when doing layout, I find myself in situations where I’d like a single galvanic connection on the board to bear multiple net names. The typical use case is when joining two different devices that are bound to have independent pin names that are each too important to omit, such as when creating a daughterboard for a well-known single-board computer.
Additionally, there are occasional times when I need to mandate or forbid certain components from being electrical neighbors on a long PCB trace. For example, when assigning bypass capacitors to specific supply pins of processors, it is conventional to place the capacitor model with the least equivalent series inductance closest to said processor. In this case, placing a net tie on either side is sensible. Additionally, passive pulse-forming networks (PFNs) occasionally benefit from similar restrictions if the components must occur in a specific order between the pulse source and destination.
TRACE-ROUTING REFINEMENTS
Often in radio frequency (RF) projects, the designer is forced to make tough tradeoffs regarding the size and routing of particular signals across the printed circuit board. The whole idea centers on qualities of the RF trace itself: its characteristic impedance (often denoted Z₀) and any companion differential traces needed to carry its complementary signal. In the case of USB and Ethernet, there is an additional requirement to ensure that signals in both differential traces have roughly the same time of flight (ToF)—a factor controlled not only by the trace’s geometry and placement, but also surrounding materials.
While later releases of each KiCad version have vastly improved its specialty trace routing (namely by reducing sluggishness and crashes), the software suite has yet to directly compete with EDA competitors.
